Power delivery is a significant concern in the design and operation of a microelectronic device. Where the microelectronic device is a processor or an application-specific integrated circuit (ASIC), an adequate current delivery, a steady voltage, and an acceptable processor transient response are desirable characteristics of the overall system. One of the methods for responding to a processor transient is to place a high-performance capacitor as close to the processor as possible to shorten the transient response time. Although a large-capacity and high-performance capacitor is preferable to answer the processor transients, the capacitor is in competition for space in the immediate vicinity of the processor. This may involve making a cutout in a portion of a board or socket to make room for the capacitor. A cutout in a board is a factor for increasing overall package size, which is counter to the trend to miniaturize. Another problem is placing the capacitor relatively far from the die, such that significant resistance exists in the decoupling signal path. Additionally, significant inductance is experienced in decoupling capacitors due to their conventional configuration.
The coefficient of thermal expansion (CTE) of materials proximate a die is also a problem. During the flip-chip assembly process, the solder balls (C4 bumps) are re-flowed in order to form an interconnect between the die and the substrate. The large CTE mismatch between die and substrate create detrimental stresses on the inner structure of the die.